Recently, die-stacking technology enables multiple layers of dynamic random-access memory (DRAM) and/or a logical die to be integrated into a vertical stack. Together with a fast interconnection, stacked memory may provide a high-bandwidth and low-latency memory subsystem.
A promising use of stacked DRAM is as a memory-side cache. Using DRAM as a cache generally requires also the implementation of a tag array. However, the whole tag overhead may be too large to be stored on-chip. For example, a 1 GB DRAM cache with 64-byte blocks can require up to 96 MB of tag storage. One approach is to store the tag entry with data in DRAM. This approach may negatively impact reliability. A bit flip in the tag may cause all data in the whole cache line to be misused because both tag and data are stored together.